In order to determine the state of a memory bit inside an array, it is common practice to compare the state of the array bit to the state of a pre-set reference. For example, a mid-point reference signal can be generated by averaging the signal from two reference bits, one in a high signal state, and one in a low signal state.
Memory devices commonly include some form of error correcting code (ECC) in the output logic circuitry. If a memory bit is disturbed from its desired state, or is otherwise read incorrectly, the ECC may be used to discover and possibly correct the memory output. It is not uncommon for reference bits to be disturbed (i.e., changed to an incorrect state) during processing, packaging, and/or at any other time. If a reference bit is disturbed from its original state, the memory bits compared to that reference bit may be subject to an unusually large number of read errors.
Prior art memory systems are incapable of efficiently recovering from the presence of one or more disturbed reference bits. Accordingly, most efforts have been centered on making memory devices more robust—i.e., lowering the rate which reference bit disturbs occurs.
Accordingly, there is a need for a memory device (e.g., a MRAM memory device) incorporating self-healing reference bit methods. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.